-----------------------------------------------
-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/20/2007
-----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY comparator_16 IS
	PORT (	in0,in1			: IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
      		q	 			: OUT STD_LOGIC
			);
END comparator_16;

ARCHITECTURE behav OF comparator_16 IS
	SIGNAL comparison : STD_LOGIC_VECTOR (15 DOWNTO 0);
	SIGNAL or_tree_l1 : STD_LOGIC_VECTOR (3 DOWNTO 0);	
BEGIN
	comparison(0) <= in0(0) XOR in1(0);
	comparison(1) <= in0(1) XOR in1(1);
	comparison(2) <= in0(2) XOR in1(2);
	comparison(3) <= in0(3) XOR in1(3);
	comparison(4) <= in0(4) XOR in1(4);
	comparison(5) <= in0(5) XOR in1(5);
	comparison(6) <= in0(6) XOR in1(6);
	comparison(7) <= in0(7) XOR in1(7);
	comparison(8) <= in0(8) XOR in1(8);
	comparison(9) <= in0(9) XOR in1(9);
	comparison(10) <= in0(10) XOR in1(10);
	comparison(11) <= in0(11) XOR in1(11);
	comparison(12) <= in0(12) XOR in1(12);
	comparison(13) <= in0(13) XOR in1(13);
	comparison(14) <= in0(14) XOR in1(14);
	comparison(15) <= in0(15) XOR in1(15);
	
	or_tree_l1(0) <= comparison(0) OR comparison(1) OR comparison(2) OR comparison(3);
	or_tree_l1(1) <= comparison(4) OR comparison(5) OR comparison(6) OR comparison(7);
	or_tree_l1(2) <= comparison(8) OR comparison(9) OR comparison(10) OR comparison(11);
	or_tree_l1(3) <= comparison(12) OR comparison(13) OR comparison(14) OR comparison(15);
	
	q <= or_tree_l1(0) OR or_tree_l1(1) OR or_tree_l1(2) OR or_tree_l1(3);	
END behav;